Due to a miniaturization of a semiconductor device, it is difficult to form a line and space pattern having a width that is below the resolution limit of lithography. In order to resolve that problem, a sidewall transferring process has been suggested.
In the related art, using the sidewall transferring process, a NAND type flash memory is manufactured by a method which will be described below. First, on a processing target film in which a tunnel insulating film, a floating gate electrode film, an inter-electrode insulating film, and a control gate electrode film are stacked on a semiconductor substrate, a mask film and a hard mask film are stacked. Next, a resist pattern for forming selection gate lines or peripheral circuits is formed on the hard mask film using a general photolithography technique and the hard mask film is etched using the resist pattern as a mask by an RIE (reactive ion etching) method and a hard mask pattern is formed. Thereafter, in a word line forming region, a line and space shaped resist pattern having a first interval is formed on the mask film using a general photolithography technique. After slimming the resist pattern, the mask film is etched using the resist pattern and the hard mask pattern as masks by the RIE method to form the mask pattern. Continuously, after conformally forming and etching back the sidewall film on the processing target film on which the mask pattern is formed, the mask pattern in the word line forming region is removed to form a closed loop shaped sidewall pattern. In the word line forming region, the processing target film is processed using the closed loop shaped sidewall pattern. In the other region than the word line forming region, the processing target film is processed using the mask pattern. By doing this, the word lines, the selection gate lines, and the peripheral circuits of the NAND type flash memory are formed.
As described above, according to the photolithography technique in the related art, it is difficult to simultaneously expose a fine pattern and a comparatively large sized pattern. Therefore, a line and space shaped pattern for forming word lines of which size is the smallest on the semiconductor device is formed using a different exposure process from a pattern for selection gate lines or peripheral circuits of which sizes are larger than that of the line and space shaped pattern.
In the above-mentioned NAND type flash memory, it is ideal to make a gap between a pattern at an end of the word lines and a pattern of the selection gate line adjacent thereto to be a gap as small as a gap between the word lines. However, it is difficult to reduce the gap to be as small as the gap between the word lines because alignment is required during the photolithography.